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DJGPP - how to make timeout in loop when interrupt disabled? (Developers)

posted by Ninho(R) E-mail, 22.04.2008, 12:42

> The KBC port - what did you mean by "refresh cycle"? Is it DRAM refresh
> period? I think this can vary for different DRAM chips.

Don't worry, it's very old 'legacy' stuff, meaning actual DRAM refresh is done thru totally different channels, you can use the PIT channel as suggested by Japheth without any fear.

Another - easy - suggestion for your original timing question, since you don't need high precision, you may check the seconds count in "CMOS" SRAM registers.



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