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MUPDF/DGJPP test release! (Users)

posted by RayeR(R) Homepage, CZ, 23.02.2011, 00:27

> - Your MTRRLFBE doesn't work on my AMD K7 CPU / SiS chipset system :-(
> It reports about found VESA 3.0, outputs the LFB address, then tells it
> failed to set the MTRRs. The diagnostic is not precise enough in the
> absence of source code or adequate app documentation :
> Are you deliberately not setting the MTRRs because, maybe, your program
> doesn't "know" they are present and Intel-compatible ? Or did "something"
> unexpected happen while trying to set the regs ? Just trying to guess...
> I've been running Mtrrlfbe under HDPMI32 in case it matters.

I don't have any running AMD machine to test it. Do you know if MTRRs on AMD are compatible to intel's? My program only chcek CPUID flags if MTRR is s upported but then it doesn't branch for intel and others. Setting of MTRRs are done via RDMSR/WRMSR (so this mean machine specific). Piece of code:


DWord phys_base_ptr_shifted=phys_base_ptr>>12; // phys_base_ptr shifted for structure usage
...
  mtrr_var_pb.phys_base=phys_base_ptr_shifted;
  mtrr_var_pb.mode=mode;               // set base and mode
  memcpy(&qw_mtrr_var_pb,&mtrr_var_pb,sizeof(qw_mtrr_var_pb)); // format structure to QWord
  vesahlp_set_msr(VESA_MTRR_VAR_BASE+j*2,&qw_mtrr_var_pb);     // write modified MSR
  mtrr_var_pm.valid=1;                 // &0xFFFFFF for 36-bit address
  mtrr_var_pm.phys_mask=(~(phys_base_ptr_shifted^(phys_base_ptr_shifted+(size_kb>>2)-1)))&0xFFFFFF;
  memcpy(&qw_mtrr_var_pm,&mtrr_var_pm,sizeof(qw_mtrr_var_pm)); // format structure to QWord
  vesahlp_set_msr(VESA_MTRR_VAR_BASE+j*2+1,&qw_mtrr_var_pm);   // write modified MSR
//  printf("Setting MTRR #%d...\n",j);

---
DOS gives me freedom to unlimited HW access.

 

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