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MUPDF/DGJPP test release! (Users)

posted by Ninho(R) E-mail, 23.02.2011, 11:43

Hiya RayeR !
>> - Your MTRRLFBE doesn't work on my AMD K7 CPU / SiS chipset system :-(
>> .....

> I don't have any running AMD machine to test it. Do you know if MTRRs on
> AMD are compatible to intel's?

Yes, binary compatible MSRs starting with K7 (at least Athlon XP; am not certain about old plain Athlons) Previously K6/K6-2/K6-3 had their own incompatible mechanisms for write allocate, write combine and like stuff...


> My program only chcek CPUID flags if MTRR is
> s upported but then it doesn't branch for intel and others. Setting of
> MTRRs are done via RDMSR/WRMSR (so this mean machine specific). Piece of
> code:
(snipped)

So this part should be OK on my CPU too.

But then what's going wrong has to be the determination of the LFB address and size. I understand you are querying the VESA BIOS, which on this box provides a false answer :=) Does the your program allow for user-provided address and size ?

From bare DOS, using turbo debugger, I've just checked the MTRRs as set by the BIOS. The range intended for video LFB appears to be 32 Megabytes at D0000000h, which are properly set in a pair of phys_MTTRRs as "type 01" memory (WC). But according to your program (and VESATEST) the VESA BIOS tells the LFB is at C0000000. Moral : don't believe VESA !

Anyway... I'm going to write my own tiny DOS proggie to enable WC on the legacy video buffer - no need for DOS extended bloat in my book.

Cheers

---
Ninho

 

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