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MUPDF/DGJPP test release! (Users)

posted by RayeR(R) Homepage, CZ, 23.02.2011, 19:33

> I had not had an incentive to look into this before, now digging a little
> further, (plain DOS) : VESA BIOS reports the LFB at C0000000h (3 Giga), and
> that is correct. But at the same time for some unfathomable reason
> AMI/SiS BIOS erroneously has pointed the appropriate MTRR (MSR 20E/20F) to
> phys address D0000000h instead of C0000000. "Plug and play" they say, let
> me laugh :=)

That's the plug and pray - the right meaning ;)
>
> Correcting the MTRR "by hand" (thanks, o my faithful TD) leads to a 7-fold
> increase in video speed measurements, using the LFB.

well, so now also mtrrlfbe works?

> I also tried to enhance video speed legacy bank switched modes by setting
> the appropraite "fixed range" MTRR at A0000 to "WC" type. Strangely, in
> this case I don't get any improvements from uncacheable to write
> combinable. Any idea why ?

I don't know exactly but it's usual.

> The other way is taking the LFB address directly from the SiS 741 (north
> bridge) registers where it resides !

But this is HW dependent that I rather avoid.

---
DOS gives me freedom to unlimited HW access.

 

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