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MUPDF/DGJPP test release! (Users)

posted by Ninho(R) E-mail, 23.02.2011, 19:50

>> Correcting the MTRR "by hand" (thanks, o my faithful TD) leads to a 7-fold
>> increase in video speed measurements, using the LFB.

> well, so now also mtrrlfbe works?

No doubt it will - I'll assert it on the next opportunity

>> I also tried to enhance video speed legacy bank switched modes by
> setting
>> the appropriate "fixed range" MTRR at A0000 to "WC" type. Strangely, in
>> this case I don't get any improvements from uncacheable to write
>> combinable. Any idea why ?

> I don't know exactly but it's usual.

Ah, this is what I wished to hear. I have a hypothesis why it could behave thus : the BS memory at A0000-BFFFF has no physical existence, the video chipset has to emulate it and the complicated (S)VGA memory organisation schemes, internally translating addresses to/from linear. In the process optimisations due to write combining are lost completely or almost so. Does it like make sense ?

>> The other way is taking the LFB address directly from the SiS 741 (north
>> bridge) registers where it resides !

> But this is HW dependent that I rather avoid.

Understandably

---
Ninho

 

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