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MUPDF/DGJPP test release! (Users)

posted by Ninho(R) E-mail, 25.02.2011, 13:40

>> VESA 3.0 SiS [16384 kB]
>> Silicon Integrated Systems Corp.
>> 6330
>> 2.49.00
>> LFB address: C0000000h
>> MTRR setting failed.
>> ______________________________________

> Well I'll have a look and provide some debug ver. Can you send me your
> email?
I'll PM you with an email address

> I don't branch code according to CPU manufacturer. I just check generic
> features flag if there's 1 in MTRR bit. similar like when you check if have
> MMX, SSE, etc...

I presume that would be CPUID std function 01 -> EDX_bit12, right ? Bit is properly SET (1) by the CPU...

>
>> turbo-debugger I made a 10 instructions long setwc.com that sets the
> LFB
>> to "write combining" on this sytem, so I'm all set-up now :)

> Does this short code also search free MTRR or you write into some fix
> chosen MTRR?

It's just a custom hack, not general purpose - although it wouldn't be difficult to extend it a little... I'm just correcting MTRRs #6 and 7, using known proper values for my hardware.

>> N.B. on the same machine "VESAtest" does set WC properly when instructed
>> to do so, and measurements are OK.

> Hm interesting. Maybe I just need to recompile mtrrlfbe with newer version
> of my lib, I didn't updated it so long. Does it works with newer
> vesatest.exe too?

Shall see...

--
N.

 

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