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marcov(R)

20.07.2009, 15:51
 

New Xeon's no A20. (Miscellaneous)

In German C'T 13 (I lag a bit) there is a small note that newer Xeon's don't support A20 anymore.

It does say that Freedos himem.sys already automatically works around this.

(we had a discussion once over recent machines' dos support once, so I thought I'd mention it)

RayeR(R)

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CZ,
20.07.2009, 20:59

@ marcov
 

New Xeon's no A20.

> In German C'T 13 (I lag a bit) there is a small note that newer Xeon's
> don't support A20 anymore.

What does it mean? I though that A20 is only one of 32 (or 36) address lines of CPU. It doesn't make sense they would released A20 pin from address bus coz it would mess up whole adressing. And about A20 control logic used in PC hardware - I though it is done by KBC (class 8042 MCU) or recetnly integrated in chipset. So I guess it is chipset incompatability (reducing legacy hardware) instead of CPU issue.

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DOS gives me freedom to unlimited HW access.

marcov(R)

21.07.2009, 11:21

@ RayeR
 

New Xeon's no A20.

> > In German C'T 13 (I lag a bit) there is a small note that newer Xeon's
> > don't support A20 anymore.
>
> What does it mean? I though that A20 is only one of 32 (or 36) address
> lines of CPU. It doesn't make sense they would released A20 pin from
> address bus coz it would mess up whole adressing. And about A20 control
> logic used in PC hardware - I though it is done by KBC (class 8042 MCU) or
> recetnly integrated in chipset. So I guess it is chipset incompatability
> (reducing legacy hardware) instead of CPU issue.

Dos is long ago for me, but:

Iirc it has to do with the HMA? If seg=<maximal> ofs=<maximal> wraps around to the first 64k (PC,XT compat) or to 1MB+64k.

The A20 gate handler is the ability to turn the carry to the A20 line (making physical addresses >1MB) on and off, originally via the kbd controller that had a free pin. Probably it is now always 1MB+64k mapped, XT compatibility gone.

But possibly himem's from older Doses could crash on trying to configure it. The fact that freedos fixes it, shows it is no problem for still maintained Doses and memory managers (open source or otherwise)

So in short, the A20 line is not just a straight line, it has a minor bit of extra logic.

RayeR(R)

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CZ,
21.07.2009, 14:58

@ marcov
 

New Xeon's no A20.

> Iirc it has to do with the HMA? If seg=<maximal> ofs=<maximal> wraps
> around to the first 64k (PC,XT compat) or to 1MB+64k.

Yes

> The A20 gate handler is the ability to turn the carry to the A20 line
> (making physical addresses >1MB) on and off, originally via the kbd
> controller that had a free pin. Probably it is now always 1MB+64k mapped,
> XT compatibility gone.

Yes, A20 pin is controlled via KBC/chipset but CPU should handle it same way as other address lines. So I don't think it is problem of CPU I would look what chipset this server board use and download spec from intel and look there...

---
DOS gives me freedom to unlimited HW access.

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