DOS ain't dead

New intel & AMD CPU changes in interrupt system (Developers)

posted by RayeR , CZ, 25.03.2021, 14:17

> I think the general idea is that Intel wants a CPU --- when handling a page
> fault, invalid instruction, etc. --- to avoid having to deal with an IDT in
> the first place. An IDT is a data structure in memory, so processing an
> interrupt through an IDT means a CPU needs to read from main memory, which
> is slow.

OK, probably good idea. I would just note that the "slow" should not be so slow as I expect IDT is cached in CPU L1/L2 cache because it's often acessed so CPU shouldn't read from slow external SDRAM...

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DOS gives me freedom to unlimited HW access.

Complete thread:

• New intel & AMD CPU changes in interrupt system - RayeR, 23.03.2021, 17:49
  • New intel & AMD CPU changes in interrupt system - tkchia, 24.03.2021, 18:29
    • New intel & AMD CPU changes in interrupt system - RayeR, 25.03.2021, 14:17