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PCI phased out? (Announce)

posted by marcov, 21.02.2011, 14:09
(edited by marcov on 21.02.2011, 16:14)

> be
> > dominated by access times to the memory hierarchy, which are much higher
> > than CPU cycles - even to/from L1 cache, where the stack top will likely
> > find its place. Thus when there is pressure on the general registers,
> PUSH
> > reg/POP reg will incur significant performance penalties and is not a
> free
> > substitute for more CPU registers :-(
>
> I disagree. We may like more registers, but that's not realistic or else
> they would've done so by now.

"They" did, and upped the register count to 16 in the 64-bit version. For both integer (R8..R15) and SSE

> I hate to always bring up the past, but if we
> (and "real" pros) lived without it all these years, it can't be that
> unbearable.
People have lived without computers for millenia, but that doesn't mean I'll toss out mine.

> > I find appalling that AMD/Intel did not build a way, be it awkward, to
> > access the enlarged 64-bit registers in X86 mode, which would have been
> so
> > immediately useful unlike the address size extensions that few
> > people require. I'm sure you could easily think of ways to enhance the
> X86
If you see what made it to endusers, it is all server processor features backported to consumer. That's why most users now have several cores idling.

64-bit is no different. Server systems, specially databases really needed more address space, and that was the whole motiviation of doing this, and the rest is extra because they had a first chance since essentially the i386 in 1985 to force backwards incompat changes. (since the opcodes needed to change to make more room for the extra register bit)

Just like with i386 they also increased the orthogonality more, so that you can now read (R/E)IP

> > binary operation encoding to allow for 64 bit operations on the 8 legacy
> > registers, and hardly less easily allow access to the new ones
> (R8->R15),
> > maybe not all at the same time, all that with minimal compatibility
> > problems in 32 bit mode. But no, they didn't even try ! Drat!
>
> Perhaps they considered MMX/SSE as a workaround, who knows.
The SSE instructions are separate. For the integer regs they needed to change existing opcodes and add an extra bit to the register encoding, something that cannot be done without breaking backwards compat.

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